/*****************************************************************************
 * Copyright (C) Gemalto M2M GmbH
 *****************************************************************************
 * Project: IMC-RIL-Driver
 *****************************************************************************
 * Author : Wireless Modules RD SW A2
 *****************************************************************************
 * $Workfile: Y:/z_ms-d/src/working/Quinn/RilDrv/FirmwareUpdate.h $
 * $Revision: /main/ms-d/5 $
 *     $Date: 2013-06-27 16:00:14 $
 *   $Author: pmackent $
 *****************************************************************************
 * Target:
 *  Microsoft Windows Mobile 5.0
 *****************************************************************************
 * Description:
 *  Gemalto IMC RIL
 *****************************************************************************
 *
 * $Log: Y:/z_ms-d/src/working/Quinn/RilDrv/FirmwareUpdate.h$ 
 * 
 * /main/ms-d/5   2013-06-27 16:00:14   pmackent 
 * Adaptions for EHS5 Rel1->Rel2 update
 *
 * /main/ms-d/4   2013-03-15 14:09:07   pmackent
 * Start introducing Java update for EHS5
 *
 * /main/ms-d/3   2012-11-26 15:21:31   pmackent
 * Adapt firmware update process for EHS5
 *
 * /main/ms-d/2   2010-12-15 10:43:50   ctna0256
 * Performed lint check
 *
 * /main/ms-d/1   2010-11-26 10:11:58   ctna0256
 * Introducing firmware update for PH8
 *
 *
*/

//////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2010 Gemalto M2M GmbH
//
// Version: 1.0
// Date:    dummy
//
//////////////////////////////////////////////////////////////////////////////

#include "resource.h"

//////////////////////////////////////////////////////////////////////////////
//
// Firmware Update
//
//////////////////////////////////////////////////////////////////////////////

// Constants

// The constants of the firmware update process depend on the chipset n use.
// 0: Qualcomm chipset (Px8 family)
// 1: Intel chipset (EHS5)
#define FWUCSET(QCT,IMC)  (s_iFWUConstSet == 0 ? QCT : IMC)

#define ATC_TIMEOUT                                    1000  // TimeoutWait (in ms) while waiting for ATC response
#define WAIT_BEFORE_START                FWUCSET(2000,1000)  // Wait time (in ms) before start of download
#define WAIT_BEFORE_START_BOOTLOADER                   3000  // Wait time (in ms) before start of download for boot loader mode
#define MAX_START_ACK_TRIES                              80  // Tries waiting for first Ack.
#define WAIT_AFTER_REOPEN                  FWUCSET(100,250)  // Wait time (in ms) after opening the COM port during re-open
#define WAIT_WAITFORTIMEOUT                               1  // Intervals to wait for timeout (on Windows: set to 0 for max. performance or 1..10 for minimum processor usage)
#define WAIT_BEFORE_BLOCK_LEN                 FWUCSET(0,20)  // Wait time (in ms) before sending block lenght word
#define WAIT_AFTER_BLOCK_LEN                   FWUCSET(0,8)  // Wait time (in ms) before sending block lenght word
#define BLOCK_TIMEOUT                                  5000  // TimeoutWait (in ms) while waiting for block transmission response
#define BLOCK_RETRIES                                    10  // Maximuim numbers of retries per block
#define ERASE_FLASH_TIMEOUT   FWUCSET(BLOCK_TIMEOUT,300000)  // Timeout for first block (erase flash block on Intel chipset)
#define MAX_FIRMWARE_DOWNLOAD_ATTEMPTS                    2  // Number of re-attemps after failed download
#define WAIT_AFTER_FIRMWARE_UPDATE                     2000  // Wait two seconds after firmware update to allow the radio to perform a reset
#define MIN_V2_BOOTLOADER                                12  // Relevant for EHS5 only: earlies bootloader version which performs block update
#define REBUILD_FFS_TIMEOUT                          300000  // Relevant for EHS5: extended timeout for 1st boot after firmware update.
#define CLEANUP_TIMEOUT                               60000  // Relevant for EHS5 only: timeout for NV block cleanup with AT^SBNW="NV",2

#define BLOCK_SIZE             (32 * 1024)
#define READ_SIZE              (BLOCK_SIZE)

#define ANSWER_OK      0x01     // See description in "Firmware Update" application note
#define ANSWER_RETRY   0x02     //
#define ANSWER_FATAL   0x03     //
#define ANSWER_BUSY    0x04     //

// Class defintion
class CFirmwareUpdate
{
public:
                    CFirmwareUpdate() { m_hFile = INVALID_HANDLE_VALUE; m_iPortType = DATA_PORT; memset(m_bBuffer, 0, BLOCK_SIZE); };
                    ~CFirmwareUpdate() {};

    BOOL            PerformFirmwareUpdate(CRilHandle *pRILHandle, COM_PORT_TYPE PortType, WCHAR *wszFileName, BOOL fNoFirmwareMode);
    BOOL            PerformJavaMidletUpdate(CRilHandle *pRILHandle, COM_PORT_TYPE PortType, char *wszJadFileName, char *strOperationParam, INT operationType);
	BOOL            TransferFile(CRilHandle *pRILHandle, COM_PORT_TYPE PortType, char *strFileName, char *strOperationParam, INT operationType);
	BOOL            OpenConfigurationFile(const WCHAR *wszConfigFilePath, ActionParamList* aplMIDlet, ATCmdList* atCmdList);

private:
    BOOL                ReadBlock(BYTE *bBuffer, WORD *wBufferLen);
    INT                 CountBlocks();
    DWORD               SerWrite(const BYTE *pbData, DWORD iNr);
    BOOL                SerGetchTimeout(BYTE *pbData, DWORD dwTimeout);
#ifdef RIL_INDICATE_FIRMWAREUPDATE
    void                SendTextToMMI(CRilHandle *pRILHandle, UINT uiTextID);
#endif
    BOOL                GetJadProperty(const char *szBufferJad, const char *szProperty, char *szJarValue, UINT nBuffer);

  HANDLE                          m_hFile;
  COM_PORT_TYPE             m_iPortType;
  BYTE    m_bBuffer[BLOCK_SIZE];
};

